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1 tm file number 9036.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil americas inc. copyright ?intersil americas inc. 2001, all rights reserved isl6550a, isl6550b, isl6550c sam (s upervisor a nd m onitor) the isl6550 is a precision, ?xible, vid-code-controlled reference and voltage monitor for high-end microprocessor and memory power supplies. it monitors various input signals, and supervises the system (typically a dc/dc converter) with its output signals. see the block diagram for reference. the isl6550 includes a 5-bit dac (digital-to-analog converter), which is programmed by the ?e vid inputs. the v oltage range of the bdac (buffered dac output) is determined by the dachi and daclo voltage levels, which are externally adjustable through the r1, r2, r3 resistor divider network. vref5 is a precision-trimmed 5v reference, and is used to set the voltage at the top of the resistor divider. programmable window comparators monitor over-voltage (ov) and under-voltage (uv) levels. the ovuvsen input, usually coming from the associated power converter device is monitored and compared with bdac; an error band is established via the r4 and r5 resistor setting on the o vuvth pin. an optional external capacitor on the uvdly pin gives a programmable delay on the uv. a high gain operational ampli?r is available at pins vopp, vopm, and v opout; it can be used as a gain stage to permit monitoring voltages that are different from the bdac levels. the pen (power supply enable) input, driven from an open- collector source, enables (when logic high) the external converter output, via the pgood or start outputs (both open-drain). they both basically indicate that the power supply is enabled (pen = high) and there are no fault conditions. there are three logic options available, which determine the start and pgood states; see the block diagram or the logic options table for more detail. the three logic options are identi?d with a suf? letter a, b, or c in the ordering information. features 12v supply operation 5v reference output 5-bit digital-to-analog converter programmable dac range, within 0.8?.0v programmable undervoltage and overvoltage thresholds, and latched fault detection optional delayed undervoltage (programmable with e xternal capacitor) undervoltage lockout (power-on-reset) status indicators (start, pgood) uncommitted operational ampli?r compatible with isl6551 full bridge controller 20 pin soic and 20 lead mlfp (5x5) packages applications ? ow er supplies for high end microprocessors and servers can be paired with the isl6551 fbc for a complete full- bridge 48v-input converter, or used independently ordering information part number temp. range ( o c) package pkg. no. isl6550aib -40 to 85 20 lead soic m20.3 isl6550bib -40 to 85 20 lead soic m20.3 isl6550cib -40 to 85 20 lead soic m20.3 isl6550air -40 to 85 20 lead mlfp l20.5x5 isl6550bir -40 to 85 20 lead mlfp l20.5x5 isl6550cir -40 to 85 20 lead mlfp l20.5x5 note: the same part numbers with a ?t suf? are available as t ape and reel. data sheet november 2001
2 pinouts 20 pin wide body soic 20 pin 5 x 5 (mlf) 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vcc v opp v opm v opout vref5 gnd o vuvth bdac da chi da clo uvdly pgood start pen o vuvsen vid0 vid1 vid2 vid3 vid4 10.3mm 12.8mm 10 9 8 7 6 5 4 3 2 1 vcc v opp v opm v opout vref5 gnd o vuvth bdac da chi da clo 11 12 13 14 15 16 17 18 19 20 uvdly pgood start pen o vuvsen vid1 vid2 vid3 vid4 vid0 5mm 5mm isl6550a, isl6550b, isl6550c
3 block diagram + - 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vcc v opp v opm v opout vref5 gnd o vuvth bdac da chi daclo uvdly pgood start pen o vuvsen vid0 vid1 vid2 vid3 vid4 threshold program 5v ref b uffered opamp uvdelay r1 r2 r3 r4 r5 uvlockout 5v 10 a to 5v 10 a to 5v (each vid pin) (por) ov uv pen: h = enable; l = disable por: h = vdd too low; l = vdd ok o v: h = over-voltage; l = ok uv: h = under-voltage; l = ok uvd: h = uv delay timed out; faul t r s latch q note: s input dominates q por ov uv uvd pen pen por q: h = fault; l = no fault q pen por q uv a note: no latch in b pen por ov pen por ov uv b faul t r s latch q note: s input dominates q por ov uv uvd pen pen por q: h = fault; l = no fault q por ov uv c uvd pen logic block see options a, b, c below uv/ov hyst: see note below note: uv/ov hysteresis = 10% note: uv/ov hysteresis = 10% note: uv/ov hysteresis = 40% st pg st pg st pg c1 (opt) r st r pg 5-bit dac _buffer dac st pg note: pin numbers shown are for the 20 lead soic package. please check pinout diagrams for mlf pin numbers. l = no time-out isl6550a, isl6550b, isl6550c
4 pin descriptions note: pin numbers refer to the 20 lead soic package. please check pinout diagrams for mlf pin numbers. vcc (positive supply voltage) pin 1 - this power pin supplies power to the ic; nominally 12v. it should be b ypassed directly to the gnd pin with a 0.1 f low esr/esl capacitor. gnd (signal ground) pin 6 - this power pin is the reference ground connection for the ic, and any circuitry that provides input/output to/from it. vid0-vid4 (dac digital input code control) pins 15-11 - these are the dac digital input control code lines. vid0 represents the least signi?ant bit (lsb) and vid4 represents the most signi?ant bit (msb). table 1 shows all of the codes, and their results. note that setting all input codes low produces the maximum voltage at bdac. the minimum voltage results when all codes are set high. logic z ero is considered system ground. a ?ated input or an input held higher than 2.0v is considered a logic one level. an internal 10 a current source pulls open vid pins to a logic high (nominal 1.6v). the pins are also ttl and lvttl compatible. pen (power supply enable) pin 18 - this digital input pin enables the external converter through the start or pgood pins. a logic high (or ?at) enables the output v oltage, and a logic low disables it. this pin has a 10 a pull- up current source, so it can interface with an open-collector or open-drain driver. when disabled, the start output is low and the pgood output is low. o vuvth (over-voltage/under-voltage threshold) pin 8 - this analog input pin is used to program the window thresholds for the ov and uv comparators. the ov-uv window is centered around the bdac voltage and can be programmed from 5% to 40% about the bdac voltage. this pins voltage sets the undervoltage threshold. internal circuitry sets the overvoltage threshold such that the two thresholds are centered about bdac, the dac output v oltage. for example, if bdac is 2.5v, and ovuvth is 2.0v (0.5v below bdac), then the internal ov threshold is 3.0v (0.5v above bdac). o vuvsen (over-voltage/under-voltage sense) pin 19 - this analog input pin is the sense voltage for under-voltage and over-voltage purposes. a resistor divider from the bdac output sets the uv level, on the ovth/uvth pin; the ic will internally mirror a similar voltage for ov, and then compare them both to the ovuvsen input. da chi (high limit of bdac voltage range) pin 9 - this analog input pin sets the high level of the bdac, and is programmed through the external 3-resistor divider (r1, r2, r3) shown in the block diagram. da clo (low limit of bdac voltage range) pin 10 - this analog input pin sets the low level of the bdac, and is programmed through the external 3-resistor divider shown in the block diagram. note: a total resistance of around 50k is optimal for r1, r2, and r3. adjust the ratios of these resistors to get the desired dachi and da clo voltage levels. uvdly (under voltage delay) pin 20 - this is an analog input/output pin. when the under-voltage threshold is e xceeded, a potential fault is detected. a capacitor tied to the uvdly pin is charged by an internal 10 ua source. the r amp time of the capacitor to the threshold voltage (5v nominal) determines the delay. (no capacitor gives essentially no delay). v opp (positive opamp input) pin 2 - this analog input pin is the positive input of the opamp. v opm (minus opamp input) pin 3 - this analog input pin is the minus input of the opamp. v opout (opamp output) pin 4 - this analog output pin is the output of the opamp. bdac (buffered digital-to-analog converter) pin 7 - this analog output pin is the output of the 5-bit dac. setting all input codes low produces the maximum voltage at bdac. the minimum voltage results when all codes are set high. see table 1 for codes. vref5 (5 volt reference voltage) pin 5 - this is an analog output pin, which provides a precision reference v oltage for setting dachi and daclo voltage levels. start pin 17 - this is an open-drain pull-down digital output pin; it is pulled low when one or more of the monitored conditions is not valid; the output goes high impedance (to be pulled high externally through a pull-up resistor or equivalent) if all conditions are met. see logic options table f or the various conditions. pgood (power good) pin 18 - this is an open-drain pull- down digital output pin; it is pulled low when one or more of the monitored conditions is not valid; the output goes high impedance (to be pulled high externally through a pull-up resistor or equivalent)) if all conditions are met. see logic options table for the various conditions. isl6550a, isl6550b, isl6550c
5 . absolute maximum ratings thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15v input, output or i/o voltage . . . . . . . . . . . .gnd -0.3v to vcc +0.3v esd rating human body model (per mil-std-883 method 3015.7) . . . . . 3kv machine model (per eiaj ed-4701 method c-111) . . . . . . .200v operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . +12v ?0% t emperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c j unction temperature range . . . . . . . . . . . . . . . . . . -40 o c to 125 o c thermal resistance ja ( o c/w) soic package (typical, note 1). . . . . . . . . . . . . . . . 65 mlf package(typical, note 2) . . . . . . . . . . . . . . . . . 33 maximum junction temperature (plastic package) . . 150 maximum storage temperature range . . . . . . . . . . . . -65 to 150 maximum lead temperature (soldering 10s) . . . . . . . 300 (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 f or details. 2. j a is measured in free air with the component mounted on a high effective thermal conductivity test board with ?irect attach?f eatures. see tech brief tb379. electrical speci?ations t a is 25 o c, and vdd = 12v, unless otherwise speci?d parameter symbol test conditions min typ max units supply current input current i in vcc = 12v 5 6 ma under-voltage lockout v cc uvlo turn-on threshold 9.2 9.4 9.9 v cc uvlo turn-off threshold 8.2 8.4 8.9 v cc uvlo threshold hysteresis 1.0 dac reference dac output error (see notes 3, 4) step size = 25mv vdaclo = 0.8v to 4.225v ibdac = 0.1ma to -1ma -2 +2 mv dac output error (see notes 3, 4) step size = 50mv vdaclo = 0.8v to 3.45v ibdac = 0.1ma to -1ma -2 +4 mv dac output error (see notes 3, 4) step size = 100mv vdaclo = 0.8v to 1.9v ibdac = 0.1ma to -1ma -2 +6 mv vref5 voltage 4.95 5.05 v vid0-vid4 input lpul (vih) 2.0 v vid0-vid4 input mpdl (vil) 0.8 v vid0-vid4 input pull-up current vvidx = 0v -15 -10 a vid0-vid4 input leakage current vvidx = 5v 1 a output settling time ?lsb error band 20 s uvdly source current -10 a sink current 10 ma threshold 5v isl6550a, isl6550b, isl6550c
6 voltage amplifier input offset voltage all conditions 3.0 mv input bias current all conditions 200 na input offset current all conditions 20 50 na open loop gain all conditions 85 db common-mode rejection ratio vin ranges from 0v to 6v 80 db power supply rejection ratio 1ma load 90 db output 2ma source or 0.2ma sink 0.15 5 v maximum output current source all -2 -7 ma maximum output current sink all 0.2 4 ma slew rate all 4 v/ s phase margin 100pf load condition 45 deg input common mode voltage 06v gain-bandwidth product all 7.4 mhz monitor circuitry input common mode range ov, uv comparators 0 6 v propagation delay ov, uv comparators 1.0 s pgood, start outputs pgood voltage low ipgood = 5.0ma 0.27 0.4 v start voltage low istart = 5.0ma 0.21 0.4 v transistor breakdown voltage all conditions 15 v transistor leakage all conditions 5 a pen input lpul (vih) 2v input mpdl (vil) 0.8 v input pull-up current pen = 0v -15 -10 a input leakage current pen = 5v 1 a ov/uv uv and ov threshold hysteresis % of (vbdac-vovuvth); logic option b 40 % uv and ov threshold hysteresis % of (vbdac-vovuvth); logic options a, c 10 % notes: 3. the total resistance of r1 + r2 + r3 of 50k ? is preferred to minimize error due to dachi and daclo input currents. choose the values within this limitation such that the voltages at dachi and daclo are those desired for the high and low limits of the programming rang e. f or example, choosing r1 and r2 to be 15k and r3 to be 20k will produce a dac range of 2.0v to 3.5v. 4. dac output error as de?ed here assumes that the voltages applied to dachi and daclo are exact. the limits include errors int roduced by source impedance up to 12.5k and dachi and daclo. the error in vdachi and vdaclo (i.e. vref5 error + external resistor divider error) must be included to arrive at the total bdac output error. electrical speci?ations t a is 25 o c, and vdd = 12v, unless otherwise speci?d (continued) parameter symbol test conditions min typ max units isl6550a, isl6550b, isl6550c
7 t able 1. digital-to-analog (dac) programming code vid4 vid3 vid2 vid1 vid0 dacout vstep = (vdachi-vdaclo)/31 11111 vdaclo 11110 vdaclo + 1*vstep 11101 vdaclo + 2*vstep 11100 vdaclo + 3*vstep 11011 vdaclo + 4*vstep 11010 vdaclo + 5*vstep 11001 vdaclo + 6*vstep 11000 vdaclo + 7*vstep 10111 vdaclo + 8*vstep 10110 vdaclo + 9*vstep 10101 vdaclo + 10*vstep 10100 vdaclo + 11*vstep 10011 vdaclo + 12*vstep 10010 vdaclo + 13*vstep 10001 vdaclo + 14*vstep 10000 vdaclo + 15*vstep 01111 vdaclo + 16*vstep 01110 vdaclo + 17*vstep 01101 vdaclo + 18*vstep 01100 vdaclo + 19*vstep 01011 vdaclo + 20*vstep 01010 vdaclo + 21*vstep 01001 vdaclo + 22*vstep 01000 vdaclo + 23*vstep 00111 vdaclo + 24*vstep 00110 vdaclo + 25*vstep 00101 vdaclo + 26*vstep 00100 vdaclo + 27*vstep 00011 vdaclo + 28*vstep 00010 vdaclo + 29*vstep 00001 vdaclo + 30*vstep 00000 vdaclo + 31*vstep = vdachi isl6550a, isl6550b, isl6550c
8 logic options option definitions a b c start pin: xxx pen input is high and vcc is above the uvlo threshold and ov condition does not exist and uvdly condition does not exist. x fault latch is not set. xx pgood pin: xxx vcc is above the uvlo threshold and uv condition does not exist and ov condition does not exist and xx pen input is high and xx fault latch is not set. x f ault latch set by: x (fault latch not used) x ov condition or uvdly condition (uv has persisted past the uvdly time-out) f ault latch reset by: x (fault latch not used) x ov condition does not exist and uvdly condition does not exist and vcc below uvlo threshold or pen input low x o vuv detection: x x x uv detect threshold = vovuvth (voltage at ovuvth pin) ov detect threshold = vbdac + (vbdac - vovuvth) uv and ov threshold hysteresis = 10% of (vbdac - vovuvth) xx uv and ov threshold hysteresis = 40% of (vbdac - vovuvth) x isl6550a, isl6550b, isl6550c
9 applications information here are some step-by-step guidelines to help set up a circuit. use the block diagram for reference. 1. use a 12v ( 10%) power supply; connect to vcc and gnd. connect a 0.1 f bypass capacitor across the pins. 2. determine the minimum and maximum dac values required. vref5 is a precision 5v buffered output; connect r1, r2, r3 as a divider, to select the upper and lower range for the dac. a total of 50k ? for the 3 resistors is recommended. the maximum for dachi is 5.0v; the minimum for daclo is 0.8v. the difference between dachi and daclo, divided by 31, determines the step size of the dac. da clo = (5v) * (r3)/(r1 + r2 + r3) da chi = (5v) * (r3 + r2)/(r1 + r2 + r3) step = (dachi - daclo) / 31 f or example, if r1 is 24k, r2 is 16k, and r3 is 10k, then daclo = 1.0v, dachi = 2.6v, and step = 0.05v 3. within the above range, select the vid code for the desired bdac output voltage. (this is typically used as a reference for a dc/dc converter system). connect the vid bits accordingly (gnd is a logic low; open/?ating or 2v and above is a logic high). 4. now that bdac is set up as the desired reference voltage, the next step is to decide how far from this voltage the system voltage (typically the dc/dc converter output) is allowed to go, before shutting down the system. select r4 and r5 to create the under-voltage threshold. r4 + r5 should total around 50k ? , so as not to load the bdac. o vuvth = bdac * (r5) / (r4 + r5). the threshold is a percentage of whatever the bdac v oltage is. if we de?e delta = (bdac - ovuvth), then the sam will take that voltage, and mirror it up, to create an internal over-voltage trip point of bdac + delta, which is the same voltage above the bdac that the uv trip point is below bdac (the trip points are symmetrical by design). f or example, if bdac is 2.5v, r5 is 40k, and r4 is 10k, then ovuvth = 2.0v. since the uv threshold is 0.5v below bdac, the internal ov threshold will be 0.5v above bdac, or 3.0v. so, if during normal operation, the converter output voltage is pulled past either trip point, the start and pgood signals will change state, and can be used to shut down the converter. note that there is also h ysteresis for both trip points; it varies with each logic option; see logic options table. if an opamp is needed to help condition or ?ter the input signal at ovuvsen, the spare one can be used. it can also be used to change the gain, if the voltage to be compared is not equal to the bdac voltage. and if the opamp is not needed here, it can still be used for any other purpose. there is an optional under-voltage delay circuit. this allows the system to ignore an excursion below the uv trip point for a short time period (for example, during a power-up sequence). when the uv trip point is e xceeded, an external capacitor (c1 to gnd) on the uvdly pin gets charged through an internal 20 a current source. if the ovuvsen input is still below the trip point when the uvdly pin reaches a nominal 5v, it will make the internal uvd signal a logic high, and the start or pgood will react accordingly. the delay time dt uses the formula i = c * dv/dt. in this case, dt = c1 * 5v/20 a. or solve for c1 = (20 a) * (dt)/5v. practical values for c range from 100pf (for 25 s) up to 0.1 f (for 25ms). 5. there is an uvlo (under-voltage lock-out); also called por (power-on-reset), so as not to be confused with the under-voltage detection. this block monitors the vdd voltage; it releases around 9.4v as the power supply turns on, and has about 1.0v of hysteresis. this b lock only affects the start and pgood outputs. 6. the logic block takes the various input and internal conditions (pen, uv, ov, uvdly, por), and combines them logically to create the start and pgood outputs. these pins require some kind of external pull-up resistor (or equivalent); the pull-ups can be to the 12v supply, or any lower voltage compatible with the external logic. the v alue of the resistors depend on the pull-up voltage, the current desired, the logic voltage levels, rise or fall time considerations, etc.; a typical value would be 5k ? . the fa ult latch is set by a combination of input conditions; it is reset by por or pen (see logic options). the advantage of the latch is that a momentary fault can be saved, and the user must do something (power down or toggle pen) to recover. but some users might call that same scenario a disadvantage. so there are three different logic options to choose from. which one is best? which logic signals should you use? it depends upon whats available in the system. the pen input is useful, for example, because it can reset the fault latch of the c version; the a version requires the user to power down to reset. but does the system have a signal available to do that function? the b v ersion doesn? use a latch; if a fault condition occurs, the start and pgood will re?ct the change; but if the f ault goes away, the outputs can potentially recover on their own. so part of the choice among the logic options is whether the system is smart enough to diagnose and correct a problem, or does it just shut everything down, and wait for help. isl6550a, isl6550b, isl6550c
10 isl6550a, isl6550b, isl6550c small outline plastic packages (soic) notes: 1. symbols are defined in the ?o series symbol list?in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m20.3 (jedec ms-013-ac issue c) 20 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.4961 0.5118 12.60 13.00 3 e 0.2914 0.2992 7.40 7.60 4 e 0.050 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n20 207 0 o 8 o 0 o 8 o - rev. 0 12/93
11 all intersil products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporations quality certi?ations can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft w are and/or speci?ations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. f or information regarding intersil corporation and its products, see www.intersil.com isl6550a, isl6550b, isl6550c micro lead frame plastic package (mlfp) 0.50 dia. d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.05 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view t op view 7 bottom view 7 5 c l c l e e e1 nx 2 nx k nx b 8 nx l 8 8 l20.5x5 20 lead micro lead frame plastic package (compliant to jedec mo-220-vhhc issue c) symbol millimeters notes min nominal max a- - 0.90 - a1 - - 0.05 - a2 - - 0.70 - a3 0.20 ref - b 0.23 0.28 0.35 5,8 d 5.00 bsc - d1 4.75 bsc - d2 2.95 3.10 3.25 7,8 e 5.00 bsc - e1 4.75 bsc - e2 2.95 3.10 3.25 7,8 e 0.65 bsc - k 0.25 - - - l 0.50 0.60 0.75 8 n202 nd 5 3 ne 5 3 p- - 0.60 - --12 - rev. 2 6/01 notes: 1. dimensioning and tolerancing per asme y14.5-1994. 2. n is the number of terminals. 3. nd is the number of terminals in the x direction, and ne is the number of terminals in the y direction. 4. controlling dimension: millimeters. converted dimensions to inches are not necessarily exact. angles are in degrees. 5. dimension b applies to the plated terminal and is measured between 0.20mm and 0.25mm from the terminal tip. 6. the pin #1 identifier exists on the top surface as an indentation mark in the molded body. 7. dimensions d2 and e2 are the maximum exposed pad dimensions for improved grounding and thermal performance. 8. nominal dimensions provided to assist with pcb land pattern design efforts, see technical brief tb389.

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